Okay so I read more and I think the headline figure (1700 times more efficient) is made up/due to a significant math error. You might want to correct the title.
The paper claims that a simulated scaled-up 8-bit version of this tech (180nm CNT transistor TPUs) could theoretically reach 1TOPS/W. That is less than the efficiency the author specifies for the google TPU (4TOPS/2W = 2TOPS/W)
Then they go on to speculate that a lower process node will probably improve that efficiency greatly (very likely true, but no figures listed in the public preview of the paper, even simulations)
The author of the article assumed (wrongly) that the actual chip they made could do 1TOPS (it’s only 3000 transistors and can only do 2-bit math), and that it consumed 295 microwatts to do so, for an efficiency of 3389TOPS/W. (roughly 1700x the 2TOPS/W of the google chip) That’s of course ludicrous.
